1. Field of Invention
This invention relates to semiconductor device and fabrication thereof, and more particularly to a data storage structure, a memory device including the floating gate in duplicates, and a process for fabricating the memory device.
2. Description of Related Art
A conventional non-volatile memory (NVM) cell includes a stacked structure of a floating gate as a data storage structure and a control gate disposed thereon, operated by injecting carriers into the floating gate and removing carriers from the floating gate.
In a typical NVM using floating gates, the floating gates of the memory cells are arranged in a 2D array, wherein the gap between two neighboring floating gates in the direction of the word lines is usually close to the limit of the lithographic resolution to increase the surface area for each floating gate as well as the gate coupling ratio (GCR) between a floating gate and the corresponding control gate.
However, when the process linewidth is small, the aspect ratio of the above gap is high so that the control gate fill-in window is small. Moreover, since the above gap is close to the limit of the lithographic resolution, the lithographic overlap window in forming the floating gates is small.